AI ChipsFutures
The AI accelerator race is becoming a three-way fight, not a Nvidia monopoly
For the past several years, Nvidia's dominance in AI training hardware has been close to total — its CUDA software ecosystem locked developers in as tightly as its silicon led on raw performance. That's starting to shift, not because any single competitor has caught up outright, but because the AI accelerator market is fragmenting into distinct use cases where different chips win.
AMD's Instinct MI400 series, shipping through 2026 and 2027, is closing the raw throughput gap for large-model training, and AMD's ROCm software stack has matured enough that major labs are running production workloads on it. Meanwhile, the hyperscalers — Google with its TPU v7, Amazon with Trainium3, and Microsoft with its Maia accelerators — are deploying custom silicon at large enough scale that a meaningful share of their own AI compute no longer touches an Nvidia GPU at all.
None of this dethrones Nvidia in the next two to three years; its data center revenue and order backlog remain enormous, and its next-generation Rubin platform is arriving on an accelerated cadence specifically to defend that lead. But the realistic near-term picture is a market where Nvidia remains the largest single supplier while ceding meaningful share at the margin to AMD and, increasingly, to chips hyperscalers design purely for their own internal workloads — a very different dynamic than the near-monopoly of 2023-2024.
PackagingFutures
Advanced packaging, not wafer fabrication, is the real capacity ceiling through 2028
For most of semiconductor history, the scarce resource was leading-edge wafer capacity — the fabs themselves. That's no longer the binding constraint for AI hardware. Today, and for at least the next several years, the harder problem is advanced packaging: the process of stacking logic dies next to high-bandwidth memory and connecting them with the dense interposers that techniques like CoWoS require.
TSMC has been expanding CoWoS capacity aggressively, but qualification timelines for new packaging lines run longer than for logic wafers, and demand from AI accelerator makers has consistently outpaced each expansion. This is why Nvidia, AMD, and others have repeatedly cited packaging — not chip fabrication — as the limiting factor on how many AI accelerators they can actually ship in a given quarter.
The near-term response is twofold: TSMC and its OSAT (outsourced assembly and test) partners are racing to add packaging capacity outside Taiwan, including new sites in the U.S. and Japan, and the industry is investing heavily in the UCIe chiplet interconnect standard so that packaging bottlenecks can eventually be worked around through more flexible, modular chip designs rather than solved purely by building more of the same capacity.
GeopoliticsFutures
Export controls are permanently reshaping — not just slowing — chip supply chains
U.S. export restrictions on advanced AI chips and semiconductor manufacturing equipment bound for China have moved past being a temporary trade dispute and into a structural feature of the industry. Chipmakers now build compliance and geographic segmentation into product roadmaps from the start, rather than treating restrictions as an occasional disruption.
The near-term effect isn't a clean bifurcation into "restricted" and "unrestricted" markets — it's a messier landscape of performance-tiered products, expanded due-diligence requirements on resellers and distributors, and rules that keep tightening around potential re-export routes through third countries. Companies selling into Southeast Asia, in particular, now face meaningfully more compliance overhead than they did even a year or two ago.
Over the next two to three years, expect continued investment in manufacturing capacity outside both Taiwan and China — in Arizona, Japan, Germany, and India — driven as much by this policy environment as by pure economics. That reshoring won't eliminate Taiwan's central role in leading-edge fabrication anytime soon, but it will meaningfully diversify where second-tier and legacy-node capacity sits.
Process NodesFutures
The march to 2nm and beyond is slowing down, not stopping
TSMC, Samsung, and Intel are all racing toward 2nm-class production, with TSMC's N2 node ramping through 2026 and Intel betting heavily on its 18A process to reclaim technical leadership. But the cadence of node transitions has visibly slowed compared to the previous decade — the gains from each new node are smaller, the cost per wafer is higher, and High-NA EUV lithography tools required for the nodes beyond 2nm cost roughly $380 million each and remain supply-constrained.
This is pushing the industry toward two responses that will define the next few years more than the node race itself. First, more manufacturers are relying on chiplet designs and advanced packaging to combine smaller, cheaper dies rather than betting everything on ever-shrinking monolithic chips. Second, architectural and packaging innovation is picking up slack that pure transistor scaling used to provide on its own.
Expect 2nm to become mainstream for flagship AI and mobile chips by 2027-2028, with node transitions beyond that stretching to a slower, more expensive cadence — meaning competitive advantage increasingly comes from packaging and system design as much as from raw process technology.
MemoryFutures
Memory bandwidth, not compute, may become AI's next hard constraint
AI accelerator compute has scaled dramatically over the past several generations, but memory bandwidth — the rate at which data can move between memory and the processor — hasn't kept pace at the same rate. High-bandwidth memory (HBM) narrows this gap by stacking DRAM directly next to the accelerator die, but HBM3E and early HBM4 output from Micron and SK Hynix is already sold out more than a year in advance.
This scarcity is starting to reshape capital allocation across the entire memory industry, with manufacturers redirecting spending away from conventional DRAM and NAND toward HBM production, tightening supply and pushing up prices across the broader memory market as a side effect.
Over the next two to three years, expect memory bandwidth — not just raw compute — to increasingly determine which AI accelerators can actually be deployed at scale, and expect continued volatility in conventional memory pricing as an indirect consequence of the AI buildout.