Straight coverage of the chips powering AI, cars, phones, and everything else — without a single dollar from the companies we cover.
What's moving in semiconductors this week.
Early silicon from Nvidia's Rubin architecture — the successor to Blackwell — is already in the hands of AWS, Microsoft, and Google engineering teams for platform validation. The accelerated timeline reflects how tightly the AI accelerator roadmap is now coupled to hyperscaler capital spending cycles, with each generation arriving in roughly 12 months instead of the historical 18-24. Rubin pairs a new GPU die with HBM4 memory and NVLink 6 interconnects, aiming to keep Nvidia's training-cluster performance lead intact as AMD's MI400 series and custom silicon from Google (TPU v7) and Amazon (Trainium3) close the gap on raw throughput.
TSMC has committed to bringing 3nm production capacity to its second Arizona fab, a shift from earlier plans that limited the U.S. site to older process nodes. The move responds directly to pressure from major customers — reportedly including Apple and Nvidia — who want leading-edge capacity outside Taiwan for supply chain resilience. Construction timelines still point to volume production landing in 2028, meaning TSMC's most advanced nodes (2nm and below) will remain concentrated in Hsinchu and Kaohsiung for the near term.
Across earnings calls this quarter, TSMC, Nvidia, and AMD have all pointed to CoWoS and similar 2.5D/3D packaging capacity — not leading-edge wafer fabrication — as the actual bottleneck limiting AI accelerator shipments. Packaging lines require specialized interposers and take longer to qualify than logic wafers, and TSMC's expansion has consistently lagged demand. Expect continued spillover to outsourced assembly and test (OSAT) players and continued urgency behind U.S. and Japanese efforts to build independent advanced packaging capacity.
New guidance expands due-diligence requirements for shipments of high-end AI GPUs routed through Malaysia, Singapore, and Vietnam, closing a pathway that had reportedly been used to reach restricted end users. Chipmakers now face added compliance overhead on export paperwork for any accelerator above a defined performance density threshold. The rule doesn't ban sales to the region outright, but distributors say it will slow order fulfillment and add cost, further reshaping how AI hardware flows through Asian supply chains.
High-bandwidth memory — the specialized DRAM stacked directly next to AI accelerator dies — remains the tightest component in the AI hardware supply chain. Both Micron and SK Hynix confirmed their HBM3E and early HBM4 output is fully allocated more than a year out, driven almost entirely by Nvidia, AMD, and custom accelerator demand. The scarcity is pushing memory makers to redirect capital spending away from conventional DRAM and NAND toward HBM, with knock-on effects for pricing across the broader memory market.
After nearly two years of inventory correction, automotive semiconductor demand is stabilizing but not snapping back. Both companies cited steady orders for power management and analog chips tied to EV powertrains, offset by continued softness in legacy internal-combustion-vehicle electronics. The mixed picture underscores how the auto chip market has bifurcated: EV-specific silicon content per vehicle keeps climbing even as overall vehicle production growth stays muted.
ASML's High-NA (0.55 numerical aperture) EUV lithography systems, which enable finer transistor patterning than standard EUV, are moving past initial installs at Intel and into wider evaluation at additional customers. The tools cost roughly $380 million each and remain in limited supply, but they're viewed as essential to reaching sub-2nm-class nodes without resorting to costly multi-patterning. Broader adoption timing will be a key signal for how the 2028-2030 process roadmap actually plays out across the industry.
The Universal Chiplet Interconnect Express (UCIe) standard, backed by Intel, AMD, Arm, TSMC, and others, continues adding members as more companies bet on modular chip design over monolithic dies. The pitch: mix-and-match chiplets from different vendors and process nodes in a single package, cutting design cost and time-to-market. Broad adoption is still early, but the standard's momentum is a leading indicator for how the industry plans to manage rising design costs at the leading edge.